1. Technical Field
The present invention relates to semiconductor memory, and more particularly, to external signal input circuits in a semiconductor memory.
2. Related Art
A semiconductor memory may have a single-rank configuration or multi-rank configuration.
The semiconductor memory may include an external signal input circuit configured to receive external signals such as a clock enable signal CKE and an impedance adjustment signal ODT.
FIG. 1A illustrates an external signal input circuit 10 of one conventional semiconductor memory having a single-rank configuration. The external signal input circuit 10 may include two input units 11 and 12 configured to buffer a clock enable signal CKE and an impedance adjustment signal ODT, respectively, to generate internal signals CKE—i and ODT—i. 
FIG. 1B illustrates an external signal input circuit 20 of another conventional semiconductor memory having a multi-rank configuration, such as two or four ranks. The external signal input circuit 20 may include four input units 21 through 24 configured to buffer first clock enable signal CKE0, second clock enable signal CKE1, first impedance adjustment signal ODT0, and second impedance adjustment signal ODT1, respectively, to generate internal signals CKE—i and ODT—i. 
Here, the first clock enable signal CKE0 and second clock enable signal CKE1 may be combined to instruct a desired rank among the multi ranks to activate the clock signal.
Furthermore, the first impedance adjustment signal ODT0 and second impedance adjustment signal ODT1 may be combined to instruct a desired rank among the multi ranks to perform impedance control.
In this case, the input units 11, 12, and 21 through 24 may be configured in the same manner. Each one of the input units may control a setup/hold time of a signal buffered by an internal buffer and may drive and output the signal.
As described above, the external signal input circuits of the conventional semiconductor memories are configured in different manners based on the rank configurations thereof, that is, the single rank and the multi ranks.
The external signal input circuit 10 for the single-rank configuration may not be used in the multi-rank configuration, and the external signal input circuit 20 for the multi-rank configuration may not be used in the single-rank configuration.